MEMS technology has advanced to provide integrated packaging of the MEMS devices or sensors. This integration advancement typically refers to processes or methods at which the packaging of the MEMS device is in the form of a protective cap which hermetically seals the device from the outside environment. Furthermore it protects the MEMS device from subsequent assembly operations such as saw cutting for singulation. The processes and methods are performed at a wafer level rather than a die level. The wafer level integration offers a more efficient and cost effective manner to package the MEMS devices. One such wafer level packaging technique is the Nasiri-Fabrication platform depicted in FIG. 1. In FIG. 1, the Nasiri-Fabrication (NF) platform uses a patented wafer-to-wafer bonding process 100 that directly integrates pre-fabricated MEMS wafers 110 to off-the-shelf complementary metal-oxide semiconductor (CMOS) wafers 120 at the wafer level. The process also simultaneously provides electric contact and hermetic sealing 130 of all MEMS elements at the wafer level.
Using the process, which uses six masks, engineered silicon on insulator (ESOI) wafer 150 is formed starting with a standard silicon handle wafer etched with targets for backside alignment (mask 1); followed by oxidation and cavity etch (mask 2). A second wafer is fusion bonded to the handle wafer and subsequently thinned to define the device layer thickness. The MEMS wafer 110 is completed by etching the device layer to form standoffs (mask 3) that define the seal ring, the electrical contacts to CMOS, and the vertical gap between the CMOS and MEMS; depositing and patterning a germanium layer (mask 4) over standoffs; and patterning (mask 5) and deep reactive ion etching the device layer to form the mechanical structure 135.
Continuing, a standard CMOS wafer is fabricated, with optional etched cavities (mask 6), if needed for larger clearance under moving MEMS structures. The MEMS wafer is bonded to the CMOS wafer using AIGe eutectic bonding between the Al on the CMOS and the Ge on the MEMS wafer at 140, for example. After bonding, a portion of the MEMS wafer is removed by conventional dicing saw cuts to expose the CMOS wire bond pads 125.
While the Nasiri-Fabrication process is ideally suited for operational environments as is proven by the success of the process today, it is often desirable to have different devices sealed at different pressures or different gas compositions when integrating multiple MEMS devices on the same chip. It will be recognized by those skilled in the art that such a need may arise where, for instance, different devices are sought to be optimized for different pressures or where different devices may require different ambient gasses or pressures (hereby referred to as ambient or ambients) to operate.
Other attempts to provide for a sealed element, such as that of U.S. Pat. No. 5,285,131 disclose steps to create a MEMS element sealed in an enclosure using two capping layers and a sacrificial layer. Similarly, U.S. Pat. Nos. 6,936,491 and 7,075,160 further disclose the addition of an insulated via to make electrical contact to the underlying silicon (the latter method not taught or required for this invention).
Unfortunately, these attempts do not overcome the challenges encountered when integrating multiple MEMS devices on a single chip, where it is often desirable to have different devices sealed at different pressures involving minimal processing steps, achieving a more predictable outcome through improved control, and having reduced requirements for the commodity of space or “real estate.” Similarly, what is desired is a system and method that overcomes these challenges and provides for two or more cavities with different pressures or requiring different ambient gasses for operation on the same chip involving a wafer bonding technique. Further what is needed is a system and method providing for the integration of such devices into an integrated CMOS-MEMS to create multi-ambient devices.